[[[ NOTE: I wrote this before I realized we haven't added any Sstc CSRs yet. Can you also add them so that this doesn't fall through the cracks? ]]]

VSTIP is altered by the Sstc extension.

19.2.2. Hypervisor Interrupt (hvip, hip, and hie) Registers
This extension modifies the description of the VSTIP/VSTIE bits in the hip/hie registers as follows:

Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enable bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and the timer interrupt signal resulting from vstimecmp (if vstimecmp is implemented). The hip.VSTIP bit, in response to timer interrupts generated by vstimecmp, is set and cleared by writing vstimecmp with a value that respectively is less than or equal to, or greater than, the current (time + htimedelta) value. The hip.VSTIP bit remains defined while V=0 as well as V=1.

This will require the function form of reset_value() on the field.

It will also require a sw_read() function for the CSR overall. Something like:

  sw_read(): |
    Bits<7> vstip_bit = 0;
    if (implemented?(ExtensionName::Sstc)) {
      if ((CSR[hvip].VSTIP == 1) | (CSR[vstimecmp].VALUE > (read_mtime() + CSR[htimedelta].DELTA)) {
        vstip_bit = 7'b1000000;
      }
    }

    Bits<3> vssip_bit = CSR[hvip].VSSIP == 0 ? 0 : 3'b100;
    # ...

    return lcofi_bit | sgeip_bit | vseip_bit | vstip_bit | vssip_bit;

sure ill add Sstc CSRs I believe these are they ?

16. "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0.0 123
    16.1. Machine and Supervisor Level Additions 123
    16.1.1. Supervisor Timer Register (stimecmp) 123
    16.1.2. Machine Interrupt Registers (mip and mie) 124
    16.1.3. Supervisor Interrupt Registers (sip and sie) 124
    16.1.4. Machine Counter-Enable Register (mcounteren) 124
    16.2. Hypervisor Extension Additions 124
    16.2.1. Virtual Supervisor Timer Register (vstimecmp) 124
    16.2.2. Hypervisor Interrupt Registers (hvip, hip, and hie) 125
    16.2.3. Hypervisor Counter-Enable Register (hcounteren) 125
    16.3. Environment Config (menvcfg/henvcfg) Support

Property sw_read() is not allowed.
getting schema error

@Shehrozkashif with just that info it's hard to give any meaningful input, can you share the sholw section where that happens?

sw_read() is a CSR property, not a CSR field property. Maybe that's why you're seeing a problem?

yes paul is right! I can define this function sw_write(csr_value) but while adding sw_read():(the function derek wants me to add ) is not in fields
sw_read() so I think I have to add it as a property not in fields ?

have to add [sw_read()] as a property not in fields ?

Correct. It should be in the YAML at the "top level" as a peer with other attributes like "name", "description", and (not to be too confusing) "fields".

Got it, I’ll move sw_read() to the top level alongside name, description, and fields.

This CSR needs a sw_read function that reflects the following (I've started a skeleton of it in the VSSIP comment):

SGEIP is read-only in hip, and is 1 if and only if the bitwise logical-AND of CSRs hgeip and hgeie is nonzero in any bit.

VSEIP is read-only in hip, and is the logical-OR of these interrupt sources:

• bit VSEIP of hvip;
• the bit of hgeip selected by hstatus.VGEIN; and
• any other platform-specific external interrupt signal directed to VS-level.

VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and any other platform-specific timer interrupt signal directed to VS-level.

VSSIP in hip is an alias (writable) of the same bit in hvip

I presume this still needs to be added.

The SCRATCH field is the full register width, so you need to split it into two attributes, one for each supported length: